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This chapter documents the backend for the Advanced RISC Machine (ARM) microprocessor family.
This module is written in 2004,2006,2010-2015 by Frank Wille and is covered by the vasm copyright without modifications.
This module provides the following additional options:
Generate code compatible with ARM V2 architecture.
Generate code compatible with ARM V3 architecture.
Generate code compatible with ARM V3m architecture.
Generate code compatible with ARM V4 architecture.
Generate code compatible with ARM V4t architecture.
Output big-endian code and data.
Output little-endian code and data (default).
Generate code for the ARM2 CPU.
Generate code for the ARM250 CPU.
Generate code for the ARM3 CPU.
Generate code for the ARM6 CPU.
Generate code for the ARM600 CPU.
Generate code for the ARM610 CPU.
Generate code for the ARM7 CPU.
Generate code for the ARM710 CPU.
Generate code for the ARM7500 CPU.
Generate code for the ARM7d CPU.
Generate code for the ARM7di CPU.
Generate code for the ARM7dm CPU.
Generate code for the ARM7dmi CPU.
Generate code for the ARM7tdmi CPU.
Generate code for the ARM8 CPU.
Generate code for the ARM810 CPU.
Generate code for the ARM9 CPU.
Generate code for the ARM9 CPU.
Generate code for the ARM920 CPU.
Generate code for the ARM920t CPU.
Generate code for the ARM9tdmi CPU.
Generate code for the SA1 CPU.
Generate code for the STRONGARM CPU.
Generate code for the STRONGARM110 CPU.
Generate code for the STRONGARM1100 CPU.
The ADR directive will be automatically converted into
ADRL if required (which inserts an additional
ADD/SUB to calculate an address).
The maximum range in which PC-relative symbols can be accessed
through LDR and STR is extended from +/-4KB to +/-1MB
(or +/-256 Bytes to +/-65536 Bytes when accessing half-words).
This is done by automatically inserting an additional ADD
or SUB instruction before the LDR/STR.
Start assembling in Thumb mode.
This backend accepts ARM instructions as described in various ARM CPU data sheets. Additionally some architectures support a second, more dense, instruction set, called THUMB. There are special directives to switch between these two instruction sets.
The target address type is 32bit.
Default alignment for instructions is 4 bytes for ARM and 2 bytes for THUMB. Sections will be aligned to 4 bytes by default. Data is aligned to its natural alignment by default.
This backend extends the selected syntax module by the following directives:
.armGenerate 32-bit ARM code.
.thumbGenerate 16-bit THUMB code.
This backend performs the following optimizations and translations for the ARM instruction set:
LDR/STR Rd,symbol, with a distance between symbol and PC larger
than 4KB, is translated to
ADD/SUB Rd,PC,#offset&0xff000 +
LDR/STR Rd,[Rd,#offset&0xfff], when allowed by the option
-opt-ldrpc.
ADR Rd,symbol is translated to
ADD/SUB Rd,PC,#rotated_offset8.
ADRL Rd,symbol is translated to
ADD/SUB Rd,PC,#hi_rotated8 + ADD/SUB Rd,Rd,#lo_rotated8.
ADR will be automatically treated as ADRL when required
and when allowed by the option -opt-adr.
For the THUMB instruction set the following optimizations and translations are done:
B<!cc> .+4 + B label.
BL instruction is translated into two sub-instructions combining
the high- and low 22 bit of the branch displacement.
Some known problems of this module at the moment:
This module has the following error messages:
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