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This backend provides the following additional options:
This backend supports the following registers:
R0
through R15
for the general purpose registers
Additionally, the register pairs
R2/R3, R3/R4, R4/R5, R6/R7, R7/R8, R8/R9, R12/R13, R13/R14,
and R15/R15
are available.
R1, R11
and R12
are reserved by the backend.
The current version generates assembly output for use with the vasm
assembler. Optionally, assembly code for the Tasking
assembler can be generated.
The default memory model corresponds to the Tasking small-memory
model with 16bit data-pointers and 32bit function-pointers.
However, the DPPx
registers have to be set up in a way to
create a linear 16bit address space (i.e. DPPx=x
).
The generated code should work on systems with c161, c163, c164, c165
and c167 microcontrollers as well as ST10 derivates. Old versions like
the c166 are not supported
The registers R1-R5
and R10-R15
are used as scratch registers (i.e. they
can be destroyed in function calls), all other registers are preserved.
R0
is used as user stack pointer. Automatic variables and temporaries
are put on the user stack. Return addresses are pushed on the system
stack.
The first 4 function arguments which have integer or pointer types
are passed in registers R12
through R15
.
Integers and pointers are returned in R4/R5
.
All other types are returned by passing the function the address
of the result as a hidden argument - so when you call such a function
without a proper declaration in scope you can expect a crash.
The elementary data types are represented like:
type size in bits alignment in bytes char 8 1 short 16 2 int 16 2 long 32 2 long long n/a n/a near pointers 16 2 far pointers 32 2 huge pointers 32 2 float n/a n/a double n/a n/a |
__interrupt
MDL/MDH
will be saved, however it is recommended
to switch to a new register bank as the gprs are
not saved.
Also, DPP0-DPP3
are not saved (the compiler does not
use them).
__interrupt(<vector>)
__interrupt
, but also places a jump-instruction
to the interrupt service at the corresponding vector table
address (needs support from library and linker file).
__section(<name>)
__rbank(<bank>)
__near
__far
__huge
__section(<name>)
__sfr(<addr>)
Example:
__sfr(0xff10) volatile unsigned int PSW; |
__esfr(<addr>)
__sfrbit(<addr>,<bit>)
Example:
__sfr(0xff10,11) volatile __bit IEN; |
__esfrbit(<addr>,<bit>)
The c16x-backend offers the following additional types:
__bit
This backend defines the following macros:
__C16X__
__C167__
__ST10__
If the `-stack-check' option is used, every function-prologue will
call the function __stack_check
with the stacksize needed by this
function in register R1
. This function has to consider its own
stacksize and must restore all registers.
Only stack-checking of the user-stack is supported. Checking the system-stack is supported by hardware.
A possible <stdarg.h> could look like this:
typedef char *va_list; va_list __va_start(void); #define __va_rounded_size(__TYPE) \ (((sizeof (__TYPE) + sizeof (int) - 1) / sizeof (int)) * sizeof (int)) #define va_start(__AP,__LA) (__AP=__va_start()) #define va_arg(__AP, __TYPE) \ (__AP = ((char *) (__AP) + __va_rounded_size (__TYPE)), \ *((__TYPE *)((__AP) - __va_rounded_size (__TYPE)))) #define va_end(__AP) ((__AP) = 0) |
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