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16 PowerPC cpu module

This chapter documents the Backend for the PowerPC microprocessor family.


16.1 Legal

This module is written in 2002-2016 by Frank Wille and is covered by the vasm copyright without modifications.


16.2 Additional options for this module

This module provides the following additional options:

-big

Select big-endian mode.

-little

Select little-endian mode.

-many

Allow both, 32- and 64-bit instructions.

-mavec, -maltivec

Generate code for the Altivec unit.

-mcom

Allow only common PPC instructions.

-m601

Generate code for the PPC 601.

-mppc32, -mppc, -m603, -m604

Generate code for the 32-bit PowerPC 6xx family.

-mppc64, -m620

Generate code for the 64-bit PowerPC 600 family.

-m7400, -m7410, -m7455

Generate code for the 32-bit PowerPC 74xx (G4) family.

-m7450

Generate code for the 32-bit PowerPC 7450.

-m403, -m405

Generate code for the IBM/AMCC 32-bit embedded 40x family.

-m440, -m460

Generate code for the AMCC 32-bit embedded 440/460 family.

-m821, -m850, -m860

Generate code for the 32-bit MPC8xx PowerQUICC I family.

-mbooke

Generate code for the 32-bit Book-E architecture.

-me300

Generate code for the 32-bit e300 core (MPC51xx, MPC52xx, MPC83xx).

-me500

Generate code for the 32-bit e500 core (MPC85xx), including SPE, EFS and PMR.

-mpwr

Generate code for the POWER family.

-mpwrx, -mpwr2

Generate code for the POWER2 family.

-no-regnames

Don’t predefine any register-name symbols.

-opt-branch

Enables translation of 16-bit branches into "B<!cc> $+8 ; B label" sequences when destination is out of range.

-sd2reg=<n>

Sets the 2nd small data base register to Rn.

-sdreg=<n>

Sets small data base register to Rn.

The default setting is to generate code for a 32-bit PPC G2, G3, G4 CPU with Altivec support.


16.3 General

This backend accepts PowerPC instructions as described in the instruction set manuals from IBM, Motorola, Freescale and AMCC.

The full instruction set of the following families is supported: POWER, POWER2, 40x, 44x, 46x, 60x, 620, 750, 74xx, 860, Book-E, e300 and e500.

The target address type is 32 or 64 bits, depending on the selected CPU model.

Default alignment for sections and instructions is 4 bytes. Data is aligned to its natural alignment by default.


16.4 Extensions

This backend provides the following specific extensions:

This backend extends the selected syntax module by the following directives:

.sdreg <n>

Sets the small data base register to Rn.

.sd2reg <n>

Sets the 2nd small data base register to Rn.


16.5 Optimizations

This backend performs the following optimizations:


16.6 Known Problems

Some known problems of this module at the moment:


16.7 Error Messages

This module has the following error messages:


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