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17 c16x/st10 cpu module

This chapter documents the Backend for the c16x/st10 microcontroller family.

Note that this module is not yet fully completed!

17.1 Legal

This module is written in 2002-2004 by Volker Barthelmann and is covered by the vasm copyright without modifications.

17.2 Additional options for this module

This module provides the following additional options:


Do not translate between jump instructions. If the offset of a jmpr instruction is too large, it will not be translated to jmps but an error will be emitted.

Also, jmpa will not be optimized to jmpr.

The pseudo-instruction jmp will still be translated.


A jmp or jmpr instruction that is translated due to its offset being larger than 8 bits will be translated to a jmpa rather than a jmps, if possible.

17.3 General

This backend accepts c16x/st10 instructions as described in the Infineon instruction set manuals.

The target address type is 32bit.

Default alignment for sections and instructions is 2 bytes.

17.4 Extensions

This backend provides the following specific extensions:

17.5 Optimizations

This backend performs the following optimizations:

17.6 Known Problems

Some known problems of this module at the moment:

17.7 Error Messages

This module has the following error messages:

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