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18 6502 cpu module

This chapter documents the backend for the MOS/Rockwell 6502 microprocessor family.


18.1 Legal

This module is written in 2002,2006,2008-2012,2014-2017 by Frank Wille and is covered by the vasm copyright without modifications.


18.2 Additional options for this module

This module provides the following additional options:

-c02

Recognize all 65C02 instructions. This excludes DTV (‘-dtv’) and illegal (‘-illegal’) instructions.

-dtv

Recognize the three additional C64-DTV instructions.

-illegal

Allow ’illegal’ 6502 instructions to be recognized.

-opt-branch

Enables ’optimization’ of B<cc> branches into "B<!cc> *+3 ; JMP label" sequences when necessary.


18.3 General

This backend accepts 6502 family instructions as described in the instruction set reference manuals from MOS and Rockwell, which are valid for the following CPUs: 6502, 65C02, 65CE02, 65C102, 65C112, 6503, 6504, 6505, 6507, 6508, 6509, 6510, 6511, 65F11, 6512 - 6518, 65C00/21, 65C29, 6570, 6571, 6280, 6702, 740, 7501, 8500, 8502, 65802, 65816.

The target address type is 16 bit.

Instructions consist of one up to three bytes and require no alignment. There is also no alignment requirement for sections and data.

All known mnemonics for illegal instructions are recognized (e.g. dcm and dcp refer to the same instruction). Some illegal insructions (e.g. $ab) are known to show unpredictable behaviour, or do not always work the same on different CPUs.


18.4 Extensions

This backend provides the following specific extensions:


18.5 Optimizations

This backend performs the following operand optimizations:


18.6 Known Problems

Some known problems of this module at the moment:


18.7 Error Messages

This module has the following error messages:


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