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19 ARM cpu module

This chapter documents the backend for the Advanced RISC Machine (ARM) microprocessor family.


19.1 Legal

This module is written in 2004,2006,2010-2015 by Frank Wille and is covered by the vasm copyright without modifications.


19.2 Additional options for this module

This module provides the following additional options:

-a2

Generate code compatible with ARM V2 architecture.

-a3

Generate code compatible with ARM V3 architecture.

-a3m

Generate code compatible with ARM V3m architecture.

-a4

Generate code compatible with ARM V4 architecture.

-a4t

Generate code compatible with ARM V4t architecture.

-big

Output big-endian code and data.

-little

Output little-endian code and data (default).

-m2

Generate code for the ARM2 CPU.

-m250

Generate code for the ARM250 CPU.

-m3

Generate code for the ARM3 CPU.

-m6

Generate code for the ARM6 CPU.

-m600

Generate code for the ARM600 CPU.

-m610

Generate code for the ARM610 CPU.

-m7

Generate code for the ARM7 CPU.

-m710

Generate code for the ARM710 CPU.

-m7500

Generate code for the ARM7500 CPU.

-m7d

Generate code for the ARM7d CPU.

-m7di

Generate code for the ARM7di CPU.

-m7dm

Generate code for the ARM7dm CPU.

-m7dmi

Generate code for the ARM7dmi CPU.

-m7tdmi

Generate code for the ARM7tdmi CPU.

-m8

Generate code for the ARM8 CPU.

-m810

Generate code for the ARM810 CPU.

-m9

Generate code for the ARM9 CPU.

-m9

Generate code for the ARM9 CPU.

-m920

Generate code for the ARM920 CPU.

-m920t

Generate code for the ARM920t CPU.

-m9tdmi

Generate code for the ARM9tdmi CPU.

-msa1

Generate code for the SA1 CPU.

-mstrongarm

Generate code for the STRONGARM CPU.

-mstrongarm110

Generate code for the STRONGARM110 CPU.

-mstrongarm1100

Generate code for the STRONGARM1100 CPU.

-opt-adr

The ADR directive will be automatically converted into ADRL if required (which inserts an additional ADD/SUB to calculate an address).

-opt-ldrpc

The maximum range in which PC-relative symbols can be accessed through LDR and STR is extended from +/-4KB to +/-1MB (or +/-256 Bytes to +/-65536 Bytes when accessing half-words). This is done by automatically inserting an additional ADD or SUB instruction before the LDR/STR.

-thumb

Start assembling in Thumb mode.


19.3 General

This backend accepts ARM instructions as described in various ARM CPU data sheets. Additionally some architectures support a second, more dense, instruction set, called THUMB. There are special directives to switch between those two instruction sets.

The target address type is 32bit.

Default alignment for instructions is 4 bytes for ARM and 2 bytes for THUMB. Sections will be aligned to 4 bytes by default. Data is aligned to its natural alignment by default.


19.4 Extensions

This backend extends the selected syntax module by the following directives:

.arm

Generate 32-bit ARM code.

.thumb

Generate 16-bit THUMB code.


19.5 Optimizations

This backend performs the following optimizations and translations for the ARM instruction set:

For the THUMB instruction set the following optimizations and translations are done:


19.6 Known Problems

Some known problems of this module at the moment:


19.7 Error Messages

This module has the following error messages:


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