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This chapter documents the Backend for the PowerPC microprocessor family.
This module is written in 2002-2016 by Frank Wille and is covered by the vasm copyright without modifications.
This module provides the following additional options:
Select big-endian mode.
Select little-endian mode.
Allow both, 32- and 64-bit instructions.
Generate code for the Altivec unit.
Allow only common PPC instructions.
Generate code for the PPC 601.
Generate code for the 32-bit PowerPC 6xx family.
Generate code for the 64-bit PowerPC 600 family.
Generate code for the 32-bit PowerPC 74xx (G4) family.
Generate code for the 32-bit PowerPC 7450.
Generate code for the IBM/AMCC 32-bit embedded 40x family.
Generate code for the AMCC 32-bit embedded 440/460 family.
Generate code for the 32-bit MPC8xx PowerQUICC I family.
Generate code for the 32-bit Book-E architecture.
Generate code for the 32-bit e300 core (MPC51xx, MPC52xx, MPC83xx).
Generate code for the 32-bit e500 core (MPC85xx), including SPE, EFS and PMR.
Generate code for the POWER family.
Generate code for the POWER2 family.
Don’t predefine any register-name symbols.
Enables translation of 16-bit branches into "B<!cc> $+8 ; B label" sequences when destination is out of range.
Sets the 2nd small data base register to Rn.
Sets small data base register to Rn.
The default setting is to generate code for a 32-bit PPC G2, G3, G4 CPU with Altivec support.
This backend accepts PowerPC instructions as described in the instruction set manuals from IBM, Motorola, Freescale and AMCC.
The full instruction set of the following families is supported: POWER, POWER2, 40x, 44x, 46x, 60x, 620, 750, 74xx, 860, Book-E, e300 and e500.
The target address type is 32 or 64 bits, depending on the selected CPU model. Floating point constants in instructions and data are supported and encoded in IEEE format.
Default alignment for sections and instructions is 4 bytes. Data is aligned to its natural alignment by default.
This backend provides the following specific extensions:
-no-regnames, the registers r0 - r31,
f0 - f31, v0 - v31, cr0 - cr7, vrsave, sp, rtoc, fp, fpscr, xer, lr, ctr,
and the symbols lt, gt, so and un will be predefined on startup and may
be referenced by the program.
This backend extends the selected syntax module by the following directives:
.sdreg <n> Sets the small data base register to Rn.
.sd2reg <n> Sets the 2nd small data base register to Rn.
This backend performs the following optimizations:
B<!cc> $+8 and a 26-bit unconditional branch.
Some known problems of this module at the moment:
This module has the following error messages:
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