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This chapter documents the backend for the MOS/Rockwell 6502 microprocessor family. It also supports the Rockwell/WDC 65C02, the Hudson Soft HuC6280 and the WDC 65802/65816 instruction sets.
This module is written in 2002,2006,2008-2012,2014-2024 by Frank Wille and is covered by the vasm copyright without modifications.
This module provides the following additional options:
Recognize all HuC6280 instructions. Includes setdp $2000, so
zero-page addressing modes will be automatically used from
$2000 to $20ff.
Same as ‘-816’. There is no difference in the instruction set.
Enables the 8/16 bit instruction set for the WDC65816/65802 and additional directives to switch loading of the accumulator and/or the index register between 8 and 16 bits. The target address size becomes 24 bits.
Automatically mask values to match their data size or the size of immediate addressing, which effectively disables any range checks on immediate and data values in the assembler and linker.
Swap meaning of < and > selectors for compatibility
with the BBC ADE assembler.
Recognize all 65C02 instructions. This excludes DTV (‘-dtv’) and illegal (‘-illegal’) instructions.
Enables the Commodore CSG65CE02 instruction set, which extends on the WDC02 instruction set.
Generate 8-bit offset instead of absolute relocations when accessing a zero- or direct-page symbol.
Recognize the three additional C64-DTV instructions.
Allow ’illegal’ 6502 instructions to be recognized.
Enables the 45GS02 instruction set for the MEGA65 computer.
Enables translation of B<cc> branches into sequences of
B<!cc> *+5 ; JMP label when necessary. BRA (DTV, 65C02)
is directly translated into a JMP when out of range.
It also performs optimization of JMP to BRA,
whenever possible.
Recognize all 65C02 instructions and the WDC65C02 extensions
(RMB,SMB,BBR,BBS,STP,WAI).
This backend accepts 6502 family instructions as described in the instruction set reference manuals from MOS and Rockwell, which are valid for the following CPUs: 6502 - 6518, 6570, 6571, 6702, 7501, 8500, 8502.
Optionally accepts 65C02 family instructions as described in the instruction set reference manuals from Rockwell and WDC. Also supports the WDC extensions in the W65C02 and W65C134.
Optionally accepts 65CE02 family instructions as described in the instruction set reference manuals from Commodore Semiconductor Group.
Optionally accepts HuC6280 instructions as described in the instruction set reference manuals from Hudson Soft.
Optionally accepts 45GS02 instructions as defined by the Mega65 project.
Optionally accepts WDC65816 insructions as described in the Programming Manual by The Western Design Center.
The target address type is 16 bits, or 24 bits in WDC65816 mode.
Instructions consist of one up to three bytes for the standard 6502 family (up to 7 bytes for the 6280) and require no alignment. There is also no alignment requirement for sections and data.
All known mnemonics for illegal instructions are optionally recognized (e.g.
dcm and dcp refer to the same instruction). Some illegal
insructions (e.g. $ab) are known to show unpredictable behaviour,
or do not always work the same on different CPUs.
Note that the WDC65816’s MVN and MVP block move instructions
require a full 24-bit address (or a label) for the source and destination,
as documented in WDC’s Programming Manual. To specify the bank only, you
have to use immediate addressing syntax. Example: mvn #$7f,#^label.
Note that some of these extensions have changed since version 1.0 of this backend. Bitstream-selectors (to get the low-byte, high-byte, etc. of an expression) are no longer available as unary operators, to avoid inconsistencies, and to better conform with classic assemblers and the official WDC syntax.
This backend provides the following specific extensions:
< selects the least significant bits which fit into the current
immediate or data field width (AKA low-byte for 8-bit data).
> selects the same, but shifts the value right by 8 bits first
(AKA high-byte for 8-bit data).
^ or ` shifts the value by 16 bits first (AKA bank-byte
for 8-bit data).
Refer to chapter 6.3.3.4 (Byte Selection Operator) of the W65C816S datasheet.
These selector prefixes are always valid, no matter if 6502 or 65816
mode is active.
See also option ‘-bbcade’, which swaps the meaning of the <
and > selectors.
lda >$12 to enforce a 16-bit instead of a zero-page address).
< enforces 8-bit (direct/zero-page) addressing.
| or ! enforces 16-bit (absolute) addressing.
> enforces 24-bit (long absolute) addressing in 65816 mode, 16-bit
otherwise.
Refer to chapter 6.3.3.5 of the W65C816S datasheet.
This backend extends the selected syntax module by the following directives:
a8Declares that immediate instructions accessing the accumulator have 8 bits width (default, WDC65816 only).
a16Declares that immediate instructions accessing the accumulator have 16 bits width (WDC65816 only).
as Alias for a8 (WDC65816 only).
al Alias for a16 (WDC65816 only).
cpu <name> Define the cpu model. Must be specified before any code is generated
and has priority over cpu settings on the command line.
Most common names are recognized, like: 65c02, wdc02,
65816, HU6280, 45gs02, 6510, etc.
<symbol> ezp <expr> Works exactly like the equ directive, but marks <symbol>
as a zero/direct page symbol and use zero page addressing whenever
<symbol> is used in a memory addressing mode.
longa on|off Turns 16-bit accumulator width on or off.
WDC-style alias for a16/a8 (WDC65816 only).
longi on|off Turns 16-bit index register width on or off.
WDC-style alias for x16/x8 (WDC65816 only).
setdp <expr> Set the current base address of the zero/direct page for
optimizations from absolute to direct-page addressing modes.
Can be set to any 16-bit address on 65816 (defaults to zero).
Is preset to $2000 for the HuC6280/PC-Engine.
x8Declares that immediate instructions accessing the index registers have 8 bits width (default, WDC65816 only).
x16Declares that immediate instructions accessing the index registers have 16 bits width (WDC65816 only).
xs Alias for x8 (WDC65816 only).
xl Alias for x16 (WDC65816 only).
zero Switch to a zero/direct page section called zero or .zero,
which has the type bss with attributes "aurwz".
Accesses to symbols from this section will default to zero page
addressing mode.
zpage <symbol1> [,<symbol2>...] Mark symbols as zero/direct page and use zero page addressing for
expressions based on this symbol, unless overridden by an addressing
mode selector (like >).
All these directives are also available in the form starting with a
dot (.).
This backend performs the following operand optimizations and translations:
B<!cc> *+5 and an absolute JMP instruction
(‘-opt-branch’).
JMP to BRA,
when ‘-opt-branch’ was given.
Some known problems of this module at the moment:
This module has the following error messages:
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